1. Field of the Invention
The present invention relates generally to semiconductor processing, and relates more specifically to the heating and cooling of wafers used to make integrated circuits.
2. Related Art
Microelectronic devices are fabricated employing multiple layers of materials formed upon suitable carriers or substrates. Many of the layers of microelectronics materials must be patterned and registered accurately to produce fine dimensions. As circuit density and performance requirements have increased, the tolerances and dimensions of the patterns have become correspondingly smaller. It is common practice to form patterns in layers of microelectronic materials employing photolithography, wherein the layer of material to be patterned is coated with a light sensitive lacquer or photoresist material, which is then exposed to a pattern of light radiation to form the latent image of the pattern in the photoresist material. This latent image is then chemically developed to form a photoresist etch mask of the pattern, which can then be transferred to the underlying material layer by additive or subtractive processes such as etching or other analogous processes.
As feature sizes in the production of integrated circuits approach 100 nm, problems of packing density become increasingly difficult to overcome. The major problem is lithographic exposure tool resolution for exposure of photoresists. Photoresists and the manipulation of photoresists are well known in the art, but a short description of some important issues follows. Photoresists are applied as a thin film coating to a suitable substrate. Upon imagewise exposure of the coated substrate to actinic radiation, the difference in solubility rates between exposed and unexposed areas produces an image on the substrate after development. The uncovered substrate is thereafter subjected to an etching process. Frequently, this involves a plasma etching against which the resist coating must be sufficiently stable. For a positive tone photoresist, the coating protects those areas of the substrate from the etchant which were covered during the exposure, and thus the etchant is only able to etch the areas which were uncovered. The photoresist coating protects the covered areas of the substrate from the etchant and thus the etchant is only able to etch the uncovered areas of the substrate. Thus, a pattern can be created on the substrate which corresponds to the pattern of the mask or template that was used to create selective exposure patterns on the coated substrate prior to development.
The ability to reproduce very small dimensions is extremely important in the production of large scale integrated circuits on silicon chips and similar components. As the integration degree of semiconductor devices becomes higher, finer photoresist film patterns are required. One way to increase circuit density on such a chip is by increasing the resolution capabilities of the resist.
The optimally obtainable microlithographic resolution is essentially determined by the radiation wavelengths used for the selective irradiation. However, the resolution capacity that can be obtained with conventional deep UV microlithography (i.e. 248 nm) has its limits. In order to be able to sufficiently resolve optically small structural elements, e.g. features of 0.13 microns and smaller, radiation of ever shorter wavelengths (particularly 193 nm) is being employed together with a new generation of chemical amplification resist films.
A typical chemical amplification photoresist film comprises a polymer, a photoacid generator, and other optional additives. The polymer is required to be soluble in the chosen developer solution, and have high thermal stability and low absorbance to the exposure wavelength in addition to having excellent etch resistance. Chemically amplified photoresists are based on chemically amplified deblocking. With this mechanism, a molecule of photogenerated acid catalyzes the breaking of bonds in a protecting group of a polymer. During the deblocking process, another molecule of the same acid is created as a byproduct, and continues the acid-catalytic deblocking cycle.
Chemically amplified resists require both an exposure dose to generate a latent acid and image and a thermal dose to drive the deblocking reaction that changes the solubility of the resist in developer. Because the photogenerated acid diffuses through the resist as it catalyzes the deblocking reaction, the acid could diffuse into unexposed regions and have a significant impact on the quality of the image generated in the resist. An important criteria of the post-exposure bake process (PEB) is optimization of the balance between the relative rates of the diffusion and reaction processes. Pre diffusion reaction processes may include photo acid loss to the environment. The post diffusion reaction processes are more specifically, the amplification reaction and the acid loss reaction. Because the diffusivity and the reaction rate are both temperature dependent, careful manipulation and monitoring of the thermal history of the resist is critical to the final dimensions of the integrated circuit. The diffusion process, the amplification reaction process, and the acid loss reaction each have different activation energies. The activation energies for diffusion and for the amplification reaction are both high, whereas the activation energy for the acid loss reaction is low in comparison.
Because of this, the ramp or rise time is critical in the formation of dense features. Lines or other features that are densely located may join together in a process known as scumming, whereas isolated lines or features exposed to the same thermal dose will increase linearly and be well resolved. At the beginning of the bake, the acid loss reaction scavenges acid before the wafer reaches a temperature that is hot enough to drive the deblocking reaction. After the hotplate temperature is reached, acid loss, diffusion and amplification occur simultaneously. Delays in reaching the bake temperature can result in substantial acid loss before deblocking can begin, contributing to the aforementioned scumming process. For more information please refer to an article by Mark D. Smith which is hereby incorporated by reference in its entirety, entitled “Modeling the impact of thermal history during post exposure bake on the lithographic performance of chemically amplified resists,” proceeding of SPIE, Vol. 4345, 1013–1021, 2001, Advances in Resist Technology and Processing XVIII.
FIGS. 1–3 illustrate a prior art oven used for post-exposure baking of silicon wafers. FIG. 1 is an exploded view of a prior art oven illustrating a top enclosure 20, gas inlet 22, showerhead 24, wafer 28, hot plate 32 with proximity pins 34, lift off pins 36 and bottom enclosure 40. FIG. 2 is a cross section of the prior art oven shown in FIG. 1 in the open position, with wafer 28 elevated from the surface of hotplate 32 and proximity pins 34. FIG. 3 is a cross section of the prior art oven shown in FIG. 1 in a closed potion, with the wafer 28 upon proximity pins 34 of hot plate 32. Showerhead 24 has passages to distribute the gas arriving from gas inlet 22. One example of such an oven is manufactured by Tokyo Electron Corporation (TEC) of Kumamoto, Japan.
Generally the proximity pins raise wafer 28 about 100–150 microns off of the surface of hot plate 32. In practice, wafer 28 cannot be made or maintained during prior processing perfectly flat, and there are differences in the degree of flatness from wafer to wafer. Because of the vertical temperature gradient within the oven, even small variations in flatness can result in a relatively large disparity in the temperature at different points across wafer 28. For example, if the wafer is concave such that the ends are further from hotplate 32 than the middle, the middle portion will be hotter than the ends. This variation may result in a rise time that differs by a factor of two at different areas of the wafer in the prior art design, and is thus detrimental to precision activation and control of the diffusion and reaction processes.